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In dem B&R Modul ist ein ASIC SPC3 verbaut, laut Chip Hersteller (Siemens):
6.2.5 Write_Read_Data / Data_Exchange (Default_SAP)
Auszug:
If the user’s evaluation cycle time is shorter than the bus cycle time, the user does not find any new buffers
with the next ‘Next_Dout_Buffer_Cmd’ in ‘N.’ Therefore, the buffer exchange is omitted, At a 12 Mbd baud
rate, it is more likely, however, that the user’s evaluation cycle time is larger than the bus cycle time. This
makes new output data available in ‘N’ several times before the user fetches the next buffer. It is
guaranteed, however, that the user receives the data last received.
Könnte die Zykluszeit auf der B&R Seite etwas damit zu tun haben?
6.2.5 Write_Read_Data / Data_Exchange (Default_SAP)
Auszug:
If the user’s evaluation cycle time is shorter than the bus cycle time, the user does not find any new buffers
with the next ‘Next_Dout_Buffer_Cmd’ in ‘N.’ Therefore, the buffer exchange is omitted, At a 12 Mbd baud
rate, it is more likely, however, that the user’s evaluation cycle time is larger than the bus cycle time. This
makes new output data available in ‘N’ several times before the user fetches the next buffer. It is
guaranteed, however, that the user receives the data last received.
Könnte die Zykluszeit auf der B&R Seite etwas damit zu tun haben?
